2 Channel Integrated Circuit Chip 500 MSPS DDS with 10-Bit DACs AD9958BCPZ

Product Specification

2-Channel 500 MSPS DDS with 10-Bit DACs                        AD9958

FEATURES

2 synchronized DDS channels @ 500 MSPS

Independent frequency/phase/amplitude control between channels

Matched latencies for frequency/phase/amplitude changes

Excellent channel-to-channel isolation (>72 dB)

Linear frequency/phase/amplitude sweeping capability

Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable)

2 integrated 10-bit D/A converters (DACs)

Individually programmable DAC full-scale currents

32-bit frequency tuning resolution

14-bit phase offset resolution

10-bit output amplitude scaling resolution

Serial I/O Port (SPI) with 800Mbps data throughput

Software-/hardware-controlled power-down

Dual supply operation (1.8 V DDS core/3.3 V serial I/O)

Multiple device synchronization

Selectable 4× to 20× REF_CLK multiplier (PLL)

Selectable REF_CLK crystal oscillator

56-Lead LFCSP

APPLICATIONS

Agile local oscillator

Phased array radar/sonar

Instrumentation

Synchronized clocking

RF source for AOTF

Single-side band suppressed carrier

Quadrature communications

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD9958 consists of two DDS cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing such as filtering, amplification, or PCB layout related mismatches. Since both channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported.

The AD9958 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9958 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

The AD9958 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPIcompatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices DDS products. Flexibility is provided by four data pins (SDIO_0:3) that allow four programmable modes of serial I/O operation.

The AD9958 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates two integrated, high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier.

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel.

The DDS acts as a high resolution frequency divider with the REF_CLK as the input and the DAC providing the output. The REF_CLK input source is common to both channels and can be driven directly or used in combination with an integrated REF_CLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REF_CLK multiplier.

The AD9958 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires the pin labeled DVDD_I/O (Pin 49) be connected to 3.3 V.

The AD9958 operates over the industrial temperature range of −40°C to +85°C.

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability