Anterwell Technology Ltd.
| Payment Terms | T/T, Western Union,PayPal |
| Supply Ability | 290PCS |
| Delivery Time | 1 Day |
| Packaging Details | please contact me for details |
| VCC | 16 V |
| TJmax | 150 °C |
| Tstg | −60 to +150°C |
| Input voltage, VI | ±22 V |
| Brand Name | MICRON |
| Model Number | MT48LC32M16A2P-75IT |
| Certification | Original Factory Pack |
| Place of Origin | Original |
View Detail Information
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Product Specification
| Payment Terms | T/T, Western Union,PayPal | Supply Ability | 290PCS |
| Delivery Time | 1 Day | Packaging Details | please contact me for details |
| VCC | 16 V | TJmax | 150 °C |
| Tstg | −60 to +150°C | Input voltage, VI | ±22 V |
| Brand Name | MICRON | Model Number | MT48LC32M16A2P-75IT |
| Certification | Original Factory Pack | Place of Origin | Original |
| High Light | programming ic chips ，ic programmer circuit | ||
MT48LC32M16A2P -75IT Programmable IC Chips , popular complex integrated circuits
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
GENERAL DESCRIPTION
The Micron® 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank;A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence.
STOCK LIST
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Company Details
Business Type:
Distributor/Wholesaler,Trading Company
Year Established:
2004
Total Annual:
500000-1000000
Employee Number:
20~30
Ecer Certification：
Site Member
King--- Originator of ANTERWELL, engaged in the IC electronics industry in 1998 and establish ANTERWELL in 2004. The company is located in Shenzhen Huaqiang North, the largest electronic center in Asia. Our main business is the technical development and ... King--- Originator of ANTERWELL, engaged in the IC electronics industry in 1998 and establish ANTERWELL in 2004. The company is located in Shenzhen Huaqiang North, the largest electronic center in Asia. Our main business is the technical development and ...
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