Robust CMOS digital isolator Broadcom HCPL-9000-500 with UL1577 and IEC 61010-1

Product Specification

Broadcom HCPL-90xx and HCPL-09xx High-Speed Digital Isolators

Product Overview

The Broadcom HCPL-90xx and HCPL-09xx series are high-speed CMOS digital isolators designed for robust performance and excellent transient immunity. Featuring a symmetric magnetic coupling barrier, these devices offer industry-leading speed with a typical pulse width distortion of 2 ns, a typical propagation delay skew of 4 ns, and a 100 Mbaud data rate. Available in single, dual, and quad-channel configurations, they are ideal for isolating data conversion devices, parallel buses, peripheral interfaces, and digital fieldbus applications. These isolators are compatible with 3.3V and 5V TTL/CMOS logic and are specified for operation over a wide temperature range of 40C to +100C.

Product Attributes

• Brand: Broadcom
• Technology: CMOS Digital Isolators
• Certifications: UL1577, IEC 61010-1

Technical Specifications

Applications

• Digital fieldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High-speed digital systems
• Isolated data interfaces
• Logic level shifting

Package Characteristics

Insulation and Safety Related Specifications

Recommended Operating Conditions

Electrical Specifications (Typical at TA = +25C)

3.3V Operation

5V Operation

Application Information

Power Consumption

The HCPL-90xx and HCPL-09xx digital isolators achieve low power consumption by detecting input logic signal edge transitions and converting them into narrow current pulses to drive the isolation barrier. The output latch then reconstructs the signal. Power consumption is frequency-dependent and independent of the mark-to-space ratio. Approximate supply current per channel: I(Input) = 40(f/f_max)(1/4) mA, where f = operating frequency and f_max = 50 MHz.

Signal Status on Start-up and Shut Down

To minimize power dissipation, input signals are differentiated and latched. This can lead to ambiguous output states during power-up, shutdown, or power loss. Designers should consider including an initialization signal in the start-up circuit by toggling the input high then low, or low then high.

Bypassing and PC Board Layout

These digital isolators are designed for ease of use with no external interface circuitry required. High-speed CMOS IC technology allows direct connection to CMOS logic inputs and outputs. For proper operation, low ESR 47 nF ceramic capacitors are recommended for power supply decoupling, placed as close as possible to the VDD pins. Ground planes for both GND1 and GND2 are highly recommended for data rates above 10 Mb/s.

Propagation Delay, Pulse Width Distortion, and Propagation Delay Skew

Propagation delay (tPLH, tPHL) measures signal transit time. Pulse Width Distortion (PWD) is the difference between tPHL and tPLH, impacting maximum data rate. Propagation Delay Skew (tPSK) and Channel-to-Channel Skew (tCSK) are critical for parallel data transmission, ensuring signal synchronization. tPSK is the difference in propagation delays between devices, while tCSK is the difference within channels of a single device. In parallel applications, the absolute minimum pulse width is typically twice tPSK to avoid data corruption.