L6563STR PFC Transition Mode PFC 5mA 90uA Electronic Integrated Circuits

Product Specification

STMicroelectronics L6599ATDTR Professional Power Management PMIC IMPROVED High Volt RESONANT CONTROLLER 

                                                                Features 

Tracking boost function ■ Fast “bidirectional” input voltage feedforward (1/V2 correction) ■ Interface for cascaded converter's PWM controller ■ Remote ON/OFF control ■ Accurate adjustable output overvoltage protection ■ Protection against feedback loop disconnection (latched shutdown) ■ Inductor saturation protection ■ Low (≤ 100 µA) start-up current ■ 6 mA max. operating bias current ■ 1% (@ TJ = 25 °C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO14 package

                                                                 Pin connection

                                                              Pin description

                                                                     Pin connection

                                                          Typical electrical performance

                                            Overvoltage protection Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 35). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected. Example: VO = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) = 51 kΩ. When this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin PFC_OK drops below 2.4 V. Notice that R1, R2, R3 and R4 can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both INV and PFC_OK pins

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