Product Specification

Silicon / Silicon Carbide (SiC) Wafer Four-Stage Linked Polishing Automation Line (Integrated Post-Polish Handling Line)

Overview

This Four-Stage Linked Polishing Automation Line is an integrated, in-line solution designed for post-polish / post-CMP operations of silicon and silicon carbide (SiC) wafers. Built around ceramic carriers (ceramic plates), the system combines multiple downstream tasks into one coordinated line—helping fabs reduce manual handling, stabilize takt time, and strengthen contamination control.

In semiconductor manufacturing, effective post-CMP cleaning is widely recognized as a key step to reduce defects before the next process, and advanced approaches (including megasonic cleaning) are commonly discussed for improving particle removal performance.

For SiC in particular, its high hardness and chemical inertness make polishing challenging (often associated with low material removal rate and higher risk of surface/subsurface damage), which makes stable post-polish automation and controlled cleaning/handling especially valuable.

What the Line Does (Core Functions)

A single integrated line that supports:

• Wafer separation and collection (after polishing)

• Ceramic carrier buffering / storage

• Ceramic carrier cleaning

• Wafer mounting (pasting) onto ceramic carriers

• Consolidated, one-line operation for 6–8 inch wafers

Key Benefits

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  Integrated automation: Separation → buffering → cleaning → mounting in one line, reducing standalone stations and operator dependency.

• Cleaner, more consistent post-polish flow: Designed to support stable post-CMP / post-polish cleanliness and repeatable mounting quality. (Industry literature highlights the importance of post-CMP cleaning to lower defectivity.)

• Automation supports contamination control: Research on wafer handling emphasizes strategies to prevent wafer surface contact and reduce particulate contamination during transfers; cleanroom robot designs also focus on minimizing particle emissions.

• 6–8 inch readiness: Helps plants operate today on 6-inch while preparing for 8-inch deployment. The industry is actively progressing toward 200 mm (8-inch) SiC, with multiple public roadmaps and announcements around 2024–2025.

Technical Specifications (From Provided Datasheet)

• Equipment Dimensions (L×W×H): 13643 × 5030 × 2300 mm

• Power Supply: AC 380 V, 50 Hz

• Total Power: 119 kW

• Mounting Cleanliness: 0.5 μm < 50 ea; 5 μm < 1 ea

• Mounting Flatness: ≤ 2 μm

Throughput Reference (From Provided Datasheet)

Configured by ceramic carrier diameter and wafer size:

• 6-inch wafers: Carrier Ø485, 6 wafers/carrier, ~3 min/carrier

• 6-inch wafers: Carrier Ø576, 8 wafers/carrier, ~4 min/carrier

• 8-inch wafers: Carrier Ø485, 3 wafers/carrier, ~2 min/carrier

• 8-inch wafers: Carrier Ø576, 5 wafers/carrier, ~3 min/carrier

Typical Line Flow 

1. Infeed / interface from upstream polishing area

2. Wafer separation & collection

3. Ceramic carrier buffering/storage (takt-time decoupling)

4. Ceramic carrier cleaning

5. Wafer mounting onto carriers (with cleanliness & flatness control)

6. Outfeed to downstream process or logistics

Target Applications

• Post-polish / post-CMP downstream automation for Si and SiC wafer lines

• Production environments that prioritize stable takt time, reduced manual operations, and controlled cleanliness

• 6-inch to 8-inch transition projects, especially aligned with 200 mm SiC roadmaps

FAQ 

Q1: What problems does this line primarily solve?
A: It streamlines post-polish operations by integrating wafer separation/collection, ceramic carrier buffering, carrier cleaning, and wafer mounting into one coordinated automation line—reducing manual touchpoints and stabilizing production rhythm.

Q2: Which wafer materials and sizes are supported?
A: Silicon and SiC, 6–8 inch wafers (per the provided spec).

Q3: Why is post-CMP cleaning emphasized in the industry?
A: Industry literature highlights that demand for effective post-CMP cleaning has grown to reduce defect density before the next step; megasonic-based approaches are commonly studied for improving particle removal.