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SMD Varistor with High Peak Reverse Voltage Rated for Effective DDR5 16Gb A-Die

China SMD Varistor with High Peak Reverse Voltage Rated for Effective DDR5 16Gb A-Die

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SMD Varistor with High Peak Reverse Voltage Rated for Effective DDR5 16Gb A-Die

MOQ： 10000PCS
Price： Negotiable
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Good Name	SMD Varistor 10D471K 470V 10%
Technology	Metal Oxide
Supply Ability	5000,000,000PCS Per Month
Production Series	SMD Varistor
Energy Resistance	A 0.02J B 0.05J
Payment Terms	T/T,Paypal,Western Union,Money gram
Maximum Current	Varies (e.g., up to several amperes)
Applications	Surge protection in electronic circuits
Delivery Time	5-7 days
Voltage Rating Dc	385V
Storagetemperature	-55 +125
Packaging Details	Bulk/Tape
Varistor Voltage Ac	175-385V
Varistor Voltage	470V+/-10%
Energy Absorption	Typically 0.1J to 10J
Insulation Resistance	Typically >100 MΩ
Terminal	Special SMT Mount
Model Number	DDR5 16Gb A-Die SDRAM
Brand Name	UCHI
Certification	SGS.MA.CTI.CQC
Place of Origin	Dongguan，Guangdong,China

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Product Specification


Good Name	SMD Varistor 10D471K 470V 10%	Technology	Metal Oxide
Supply Ability	5000,000,000PCS Per Month	Production Series	SMD Varistor
Energy Resistance	A 0.02J B 0.05J	Payment Terms	T/T,Paypal,Western Union,Money gram
Maximum Current	Varies (e.g., up to several amperes)	Applications	Surge protection in electronic circuits
Delivery Time	5-7 days	Voltage Rating Dc	385V
Storagetemperature	-55 +125	Packaging Details	Bulk/Tape
Varistor Voltage Ac	175-385V	Varistor Voltage	470V+/-10%
Energy Absorption	Typically 0.1J to 10J	Insulation Resistance	Typically >100 MΩ
Terminal	Special SMT Mount	Model Number	DDR5 16Gb A-Die SDRAM
Brand Name	UCHI	Certification	SGS.MA.CTI.CQC
Place of Origin	Dongguan，Guangdong,China
High Light	SMD Varistor for DDR5 SDRAM ，High peak reverse voltage varistor ，SMD Varistor with A-Die compatibility

DDR5 16Gb A-Die SDRAM

1.1 Key Features

• JEDEC Standard Compliant;

• Power Supply: VDD/VDDQ = 1.1V (1.067V (-3%) to 1.166V (+6%));

• Power Supply: VPP = 1.8V (1.746V (-3%) to 1.908V (+6%));

• JEDEC standard package: 82-ball FBGA for x4/x8, 102-ball FBGA for x16;

• Array Configuration:

• 32banks(8 bank groups, 4 banks for each bank group) for x4/x8;

• 16banks(4 bank groups, 4 banks for each bank group) for x16;

• 16n-bit prefetch architecture;

• Burst Length (BL): BL16, BC8 OTF, BL32(Optional), BL32 OTF(Optional) are supported; • Programmable CAS Latency (CL);

• Programmable CAS Write Latency (CWL);

On-Die Termination (ODT) via Mode Register setting: RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD, DQS_RTT_PARK

Same Bank Refresh and All Bank Refresh for Normal Refresh Mode and Fine Granularity Refresh Mode; • Fine granularity refresh 2x (0°C ≤ TCase ≤ 85°C), 4x (85°C ≤ TCase ≤ 95°C) mode for smaller tRFC;

• Bi-directinal Differential Data-Strobe;

• POD(Pseudo Open Drain) interface for data input/output, command and address input;

• Connectivity Test Mode(TEN) is supported;

• Internal VREF for data inputs, command/address inputs and chip select;

• CAI(Command Address Inversion);

• 1N/2N Mode is supported for Commands;

• 4-tap Decision Feedback Equalizer(DFE) is supported;

• Loopback and bit Error Rate Test are supported;

• hPPR/sPPR is supported; sPPR Do/undo/Lock is supported;

• Training Modes:

• VrefDQ / VrefCA / VrefCS Training

• Read Training Mode

• CA Training Mode

• CS Training Mode

• Per Pin VREFDQ Training

• Write Leveling Training Mode

• Duty Cycle Adjuster (DCA) for Read - Global

• Per Pin DCA(Duty Cycle Adjuster) for Read - Per Pin(DQ) • Per DRAM Addressability (PDA);

• Maximum Power Saving Mode (MPSM);

• Multi-Purpose Command (MPC);

• Asynchronous reset for power up;

Operating case temperature: 0°C ≤ TCase ≤ 95°C;

• Support auto-refresh and self-refresh mode;

• Average Refresh Period:

• 3.9 μs/32ms, 8K cycles at 0°C ≤ TCase ≤ 85°C; • 1.95 μs/16ms, 8K cycles at 85°C < TCase ≤ 95°C;

Programmable Read/Write preambles and postambles;

• Cyclic Redundancy Code (CRC) is supported for Read/Write Data Integrity; • On-Die ECC;

• ECC Transparency and Error Scrub;

• MBIST / mPPR;

• Gear Down Mode is not supported;

• Package Output Driver Test Mode;

• Partial Array Self Refresh(PASR) is not supported;

• RoHS compliant

Note:

The functionality described and the timing specifications included in this datasheet are for the DLL Enabled mode ofoperation (normal operation), unless specifically stated otherwise.

DDR5 SDRAM Package Specifications

This chapter will mainly introduce the package dimension and ballout in x4/x8/x16 configurations which may help to match your device.

DDR5 SDRAM Package Dimension on Page 7

• DDR5 SDRAM x8 Ballout Using MO-210-AN – 82-ball on Page 8 • Pinout Description on Page 9

Company Details

Bronze Gleitlager

Bronze Sleeve Bushings

and

Graphite Plugged Bushings

from Quality China Factory

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Business Type:

Manufacturer,Exporter 
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Year Established:

2006 
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Total Annual:

1,500,000-2,500,000
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Employee Number:

138~168 
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Ecer Certification：

Verified Supplier 

Uchi was established in 2006 in Dongguan, China. After years of development, Uchi has become a large scale hi-tech enterprise that specialized in development and production of complete series of MOV,PTC, NTC series, PPTC series, Fuse(ALL TYPE),Resistor、integrated circuit 、 Capacitor, ... Uchi was established in 2006 in Dongguan, China. After years of development, Uchi has become a large scale hi-tech enterprise that specialized in development and production of complete series of MOV,PTC, NTC series, PPTC series, Fuse(ALL TYPE),Resistor、integrated circuit 、 Capacitor, ...

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Guangdong Uchi Electronics Co.,Ltd
Room 810, Unit 2, Building 5, Huixing Commercial Center, Dongsheng Road No.1, Zhongshan Dong, Shilong Town Dongguan, GUANGDONG, 523326 CN
https://www.uchidg.com/

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