Ultra Small 0.40mm Bare Die Radiation Hardened 47pF 50V MOS Capacitor Zero

Product Specification

HACC470S50V160 Ultra-Small Radiation Hardened MOS Capacitor 47pF 50V Zero Piezoelectric Noise Bare Die Chip

The HACC470S50V160 is a 47pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on high-resistivity float-zone silicon (>1000 Ω·cm) with 300nm thermally-grown amorphous SiO₂ dielectric. With an ultra-miniature footprint of just 0.40 * 0.40 * 0.15mm (16mil * 16mil * 6mil) — a 36% area reduction versus standard 0.50mm chips — this device enables capacitor integration into the most extreme space-constrained RF hybrid microcircuits, phased-array beamformer tiles, and satellite payload modules where every square micron of carrier real estate is critical.

1. Ultra-Small 0.40mm Footprint & Low-Profile Bare Die

At 0.40 * 0.40mm, the HACC470S50V160 occupies just 0.16mm² of carrier area — compared to the standard 0.50mm MOS capacitor footprint (0.25mm²). The 0.15mm (6mil) ultra-low profile is half the height of a standard 0402 MLCC (0.30mm profile) and fits within the tightest hermetic module lid clearances. This extreme miniaturization is achieved through advanced photolithography electrode definition on the single-layer MOS platform. Despite the compact size, the 2.5µm minimum gold top electrode provides a reliable wire bond pad with >6gf pull strength (25µm Au wire, thermosonic ball bonding), and the top ceramic border margin provides a clear optical reference for automated wire bonder vision systems. The full perimeter un-metallized margin is an integral ceramic feature — not an applied coating — and cannot be scratched, dissolved, or thermally degraded.

2. Zero Piezoelectric Noise — Amorphous SiO₂ Dielectric

Piezoelectric noise in capacitors is a well-documented failure mechanism in vibration-exposed electronics: mechanical strain induces a voltage through the direct piezoelectric effect (strain → polarization), modulating capacitance and introducing spurious signals into sensitive RF paths. The HACC470S50V160 eliminates this mechanism at the material level through its amorphous SiO₂ dielectric:

• No crystallographic piezoelectricity: Piezoelectricity requires a non-centrosymmetric crystal structure. Amorphous SiO₂ lacks long-range crystallographic order entirely — the random atomic network of amorphous silica cannot satisfy the symmetry conditions required for piezoelectric response.
• Zero ferroelectric domains: Unlike barium titanate (BaTiO₃) in X7R/X5R MLCCs, SiO₂ has no ferroelectric component. No domain wall motion means no mechanical-to-electrical coupling, zero singing capacitor effect, and zero microphonic noise pickup.
• Vibration test verified: Per IEC 60749 vibration test method, the HACC470S50V160 produces no measurable output above the instrumentation noise floor at 10g peak acceleration, 20Hz–2kHz sweep. This is a direct measurement result, not a theoretical prediction.
• Electrostriction comparison: The electrostrictive coefficient of thermal SiO₂ is below 10⁻²² m²/V² — approximately one million times smaller than BaTiO₃-based dielectrics (≈10⁻¹⁶ m²/V²).

3. Radiation Hardened — >100 krad(Si) TID per ESCC 22900

Total Ionizing Dose (TID) radiation degrades standard MOS structures through interface trap generation and fixed oxide charge accumulation, which shift threshold voltage and cause capacitance drift. The HACC470S50V160 uses a radiation-hardened nitrided SiO₂ gate oxide formulation specifically designed to minimize these effects:

• TID hardness >100 krad(Si): Verified per ESCC 22900 basic specification for space-grade passive components. Post-irradiation capacitance shift maintained below 5% at maximum TID.
• Post-irradiation annealing stability: <1% additional capacitance shift after 168 hours at 100°C anneal, confirming stable oxide trap passivation.
• Single Event Effects (SEE) immune: As a two-terminal passive device, the MOS capacitor has no latch-up path, no SEU-sensitive storage node, and single event gate rupture (SEGR) is prevented by the 300nm dielectric thickness. SEE immunity is verified by design — not by sample testing — providing guaranteed immunity across the full lot.
• Radiation-stable capacitance: COG/NPO paraelectric dielectric with TCC of 0 ±30 ppm/°C is intrinsically radiation-stable — no ferroelectric domain disruption mechanism exists to cause capacitance shift under irradiation.

4. Electrical Specifications (T = 25°C unless noted)

5. Assembly Quick Reference

• Die Attach: AuSn eutectic solder (300–320°C, N₂/H₂) or conductive Ag epoxy (Epotek H20E, 120°C/30min). Pt backside barrier ensures universal compatibility.
• Wire Bonding: 18µm or 25µm Au thermosonic ball bonding (120–150°C stage, 15–35gf force, >6gf typical pull strength). Ceramic margin provides visual alignment reference.
• Storage: Waffle pack or gel-pak, nitrogen cabinet at 20–25°C, 40–60% RH. MSL 1 unlimited floor life.

6. Typical Applications

• LEO/MEO/GEO satellite payload DC blocking and RF bypass in ultra-compact phased-array beamformer tiles
• Deep-space probe RF subsystems requiring TID >100 krad(Si) and zero mechanical noise susceptibility
• Radiation-environment hybrid microcircuits where 0.40mm footprint enables integration between closely-spaced GaAs/GaN MMICs
• High-reliability avionics RF front-ends operating under simultaneous vibration and radiation exposure
• Scientific instrumentation charge-sensitive preamplifiers requiring zero piezoelectric output and radiation-stable capacitance

Contact us for evaluation samples with full S-parameter data (1–20GHz), TID radiation test reports per ESCC 22900, vibration test data per IEC 60749, or custom capacitance values on the 0.40mm ultra-small platform.