Custom High Q Ultra-Low ESL 470 pF MOS Capacitor Wire Bondable Single Layer Chip

Product Specification

HACC471S20V500 Custom High Q Ultra-Low ESL MOS Capacitor 470pF 20V Wire-Bondable Single Layer Chip

The HACC471S20V500 is a high-performance, fully customizable Single Layer MOS capacitor fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO₂ dielectric. Rated at 470pF ±10% with 20V DC continuous operating voltage, this device combines High Q factor, Ultra-Low ESL/ESR, Exceptional Capacitance Stability, and Wire-Bondable Top Contact in a compact 0.50*0.50*0.15mm chip-scale package. The Double-Sided Bordered (Margin) architecture prevents conductive epoxy shorts during die attach while providing a clear visual reference for automated wire bonder alignment. Available as a standard catalog product with full customization options for capacitance value, tolerance, voltage rating, chip geometry, and backside metallization to match your specific RF circuit requirements.

Key Performance Advantages

1. High Q Factor & Ultra-Low ESL/ESR for RF Performance

The single-layer coaxial current path architecture fundamentally eliminates the parasitic inductance and resistance mechanisms that degrade MLCC performance at GHz frequencies. Current flows vertically from the top gold electrode through the SiO₂ dielectric to the backside ground plane — a path length of just 0.15mm with no internal electrodes, no vias, and no serpentine routing.

• Q Factor: >2000 at 1MHz, >200 at 1GHz — ensuring minimal signal loss in impedance matching networks
• Intrinsic Chip ESL: <0.05nH — 10* lower than equivalent-capacitance 0402 MLCC
• ESR at 1GHz: <0.1 Ohm — 5-15* improvement over comparable MLCCs
• Self-Resonant Frequency (SRF): >2GHz chip-level, >800MHz system-level with single 25µm bond wire
• Dissipation Factor: ≤0.15% at 1kHz — less than 0.15% of RF energy converted to heat

At gigahertz frequencies, capacitor Q becomes the dominant loss mechanism in impedance matching networks. The HACC471S20V500's ultra-low ESR ensures that in a 5G n77 (3.3-4.2GHz) power amplifier output match, the capacitor recovers 0.3-0.8dB of through-loss per matching element compared to an equivalent-capacitance MLCC — a critical advantage for meeting transmitter efficiency targets.

2. Exceptional Capacitance Stability over Temperature & Voltage

Class I COG/NPO (C0G/NP0) paraelectric ceramic dielectric provides consistent stability under all operating conditions:

• Temperature Coefficient (TCC): 0 ±30 ppm/°C across -55°C to +125°C — capacitance variation below ±0.3% across the full operating temperature range. 50* more stable than X7R (±15%)
• DC Bias Voltage Coefficient (VCC): <10 ppm/V — near-zero capacitance shift from 0V to full 20V rated voltage. Unlike X7R/X5R dielectrics that lose 30-80% of rated capacitance under DC bias, COG/NPO maintains consistent bypass impedance under all bias conditions
• Zero Aging Effect: No ferroelectric domains — capacitance measured today equals capacitance measured in 10 years. Class II dielectrics degrade 3-5% per decade-hour
• Low Dielectric Absorption: <0.1% — negligible memory effect in sample-and-hold and precision integrator circuits

For bias tee, VCO tank, and active bias network designs, this stability eliminates the need for complex temperature compensation varactor tuning and bias-dependent capacitance derating tables.

3. Wire-Bondable Top Contact for Chip-Scale Packaging

The top electrode features an advanced multi-layer sputtered thin-film metallization stack — TaN/TiW/Ni/Au with minimum 2.5µm gold thickness — engineered specifically for reliable, high-yield thermosonic wire bonding:

• Thick 2.5µm Au Bond Surface: Ductile gold layer absorbs 40-100mW ultrasonic bonding energy, distributing it across the full pad area without transmitting damaging stress to the ceramic substrate — eliminating bond-through/cratering failure modes
• Wide Process Window: Compatible with 25µm Au thermosonic ball bonding (120-150°C stage, 15-35gf force, 40-80mW ultrasonic) and 25µm Al ultrasonic wedge bonding
• Bond Pull Strength: >6gf typical for 25µm Au wire — exceeds MIL-STD-883 Method 2011.7 requirements per wafer lot qualification
• TaN Adhesion Layer: Ultra-robust chemical bond to ceramic dielectric prevents electrode delamination under rapid thermal cycling (-55°C to +125°C, ΔT=180°C)
• Ni Barrier Layer: Prevents gold leaching into lead-free solders during eutectic die attach reflow

The Double-Sided Bordered architecture places an un-metallized ceramic margin around both top and bottom electrodes, providing epoxy containment during die attach and a clear optical reference for automated bonding — eliminating orientation requirements during pick-and-place.

Customization Platform — Design to Your Specification

The HACC471S20V500 is built on a configurable MOS capacitor platform. We offer full customization of the following parameters with rapid prototyping turnaround:

Technical Specifications

Typical Applications

• 5G NR FR1/FR2 Power Amplifier DC Blocking & Impedance Matching
• GaN-on-SiC HEMT Bias Network Decoupling (28-50V drain supply)
• Phased-Array T/R Module Inter-stage Coupling & Bypass
• Optical Transceiver DC Blocks (100G/400G/800G QSFP-DD, OSFP)
• VCO Tank Circuits & Precision Resonator Networks
• Automotive Radar & V2X RF Front-Ends (76-81GHz)
• Satellite Communication L-Band through Ka-Band Payloads

Assembly Quick Reference

• Die Attach: Conductive silver epoxy (Epotek H20E, 120°C/30min cure) or AuSn eutectic (300-320°C, N₂/H₂). Bottom Pt barrier ensures compatibility with all methods
• Wire Bonding: 25µm Au thermosonic ball bonding (120-150°C stage, 15-35gf force, 40-80mW ultrasonic) or 25µm Al wedge bonding at room temperature
• Bond Clearance: Bond landing ≥25µm from electrode edge. Ceramic margin provides optical reference
• Storage: Waffle pack or gel-pak in nitrogen cabinet at 20-25°C, 40-60% RH. MSL 1: unlimited floor life

Contact us today with your target specifications. Standard 470pF evaluation samples ship within 1-2 weeks. Custom capacitance values, voltage ratings, chip geometries, and metallization options available with 3-4 week prototyping lead time. Full RoHS, REACH, and halogen-free compliance documentation provided per production lot.