Miniaturized High-Density 220pF 30V MOS Capacitor Exceptional High-Frequency

Product Specification

HACC221S30V120 Miniaturized High-Density MOS Capacitor: 220pF 30V with Exceptional High-Frequency Stability and Wafer-Level Customization

The HACC221S30V120 is a 220pF ±10% single-layer MOS capacitor rated at 30V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric. With an ultra-miniature footprint of just 0.35 x 0.35 x 0.15mm — a 51% area reduction versus standard 0.50mm chips — this device achieves an industry-leading capacitance density of 1796pF/mm² while maintaining exceptional high-frequency stability with chip-level SRF exceeding 2GHz. The TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au, Pt diffusion barrier) provide reliable wire bonding and universal die-attach compatibility. Fully customizable through wafer-level design: capacitance, voltage rating, die geometry, metallization stack, and multi-capacitor array configurations are all tailored to your specifications with OEM support from prototype to volume production.

1. Miniaturized High-Density Design — 1796pF/mm² in 0.35mm Footprint

The relentless drive toward smaller, lighter, and more integrated RF modules demands capacitors that deliver maximum capacitance in minimum area. The HACC221S30V120 achieves this through advanced photolithography and precision wafer fabrication:

• 0.35 x 0.35mm footprint (0.1225mm²) — 51% smaller than the industry-standard 0.50mm MOS capacitor (0.25mm²). Fits between closely-spaced GaAs and GaN MMICs on dense phased-array beamformer tiles, enabling higher channel density without carrier area expansion.
• 1796pF/mm² capacitance density — 220pF in 0.1225mm² delivers 2x the areal capacitance of standard 100pF/0.50mm MOS capacitors (400pF/mm²). Achieved through optimized electrode geometry that maximizes active capacitor area as a fraction of total die area.
• 0.15mm ultra-low profile — Half the height of an 0402 MLCC (0.30mm). Fits within hermetic module lid clearances and enables 3D-stacked hybrid assembly where vertical space is at a premium.

2. Exceptional High-Frequency Stability — SRF >2GHz for mmWave Applications

At millimeter-wave frequencies, capacitor self-resonance becomes the dominant performance limiter. The HACC221S30V120 achieves exceptional high-frequency stability through its single-layer coaxial architecture and minimized parasitic inductance:

• Chip-Level SRF: >2GHz — De-embedded measurement confirms self-resonance above typical MLCC limits (600-800MHz) and well into microwave frequencies. This is achieved through the single-layer current path with no internal electrodes, no vias, and no serpentine routing — eliminating the parasitic inductance mechanisms that limit MLCC SRF to 600-800MHz.
• System SRF with 0.5mm bond wire: >500MHz — Adequate for sub-6GHz 5G NR, satellite L/S-band, and Wi-Fi 6E bypass applications. For higher frequencies, parallel bond wires or ribbon bonding push system SRF beyond 800MHz.
• Intrinsic Chip ESL: <0.03nH — 15-20x lower than equivalent-capacitance MLCC in 0402 package (0.4-0.6nH). The ultra-low ESL ensures the capacitor maintains capacitive behavior (impedance decreasing with frequency) through substantially higher frequencies than MLCC alternatives.
• ESR <0.08 Ohm at 1GHz — Minimizes I²R losses in impedance matching networks. In a 5G n77 PA output match, this recovers 0.3-0.8dB of through-loss compared to an equivalent MLCC.

3. Wafer-Level Customization and OEM Support — Design to Your Specification

The HACC221S30V120 is built on a configurable wafer-level MOS capacitor platform. Unlike catalog-only suppliers, we offer full OEM customization from wafer fabrication to final test:

• Custom Capacitance Values: 5pF to 1000pF on the 0.35mm platform, with ±5% or tighter tolerance. Laser-trimmable to 0.1pF resolution for precision tuning applications.
• Custom Die Geometries: Rectangular aspect ratios up to 4:1, irregular shapes (L-shape, annular) for non-standard hybrid circuit footprints, and multi-capacitor array configurations (2-8 channels).
• Custom Metallization: Top: TiW-Au (standard), Al-metallized, or AuSn pre-deposition. Backside: TiW-Pt-Au (standard), Au-only, AuSn, AuGe, or AuSi for specific assembly processes.
• Wafer-Level Delivery Options: Full wafer (probed, inked, mapped), sawn wafer on frame, gel-pak trays with vacuum release, waffle packs with KGD maps, or tape-and-reel for automated assembly.
• 100% Wafer-Level Test: Every die undergoes DC parametric test (capacitance, leakage, DWV) and RF S-parameter characterization from 100MHz to 20GHz. Digital KGD wafer maps and SPC process control (CpK >1.67) provided per lot.
• Prototype-to-Production Continuity: Same wafer fabrication process, same test program, same quality standards from prototype (MOQ 10 pieces) through volume production. No process migration, no requalification.

Key Features

• Miniaturized High-Density: 0.35mm footprint, 1796pF/mm² density, 0.15mm profile — enables 51% area reduction vs. standard 0.50mm MOS capacitors
• Exceptional High-Frequency Stability: >2GHz chip SRF, <0.03nH ESL, <0.08 Ohm ESR — maintains capacitive behavior through mmWave frequencies
• Wafer-Level Customization: Custom capacitance, voltage, geometry, metallization, and array configurations from prototype to volume
• Full OEM Support: Design collaboration from specification through qualification, 100% wafer-level tested with KGD wafer maps and SPC data per lot
• SiO2 Dielectric Stability: Paraelectric with zero ferroelectric aging, zero DC bias capacitance droop, and +35ppm/°C TCC

Electrical Specifications (T = 25°C unless noted)

Typical Applications

• 5G FR2 mmWave phased-array beamformer tiles requiring maximum channel density and chip SRF >2GHz for microwave bypass and coupling
• Multi-channel satellite communication payloads (LEO/MEO) where 51% smaller footprint enables 2x channel count per carrier area
• High-density hybrid microcircuits integrating capacitors between closely-spaced GaAs/GaN MMICs
• Automotive radar MMIC bias networks requiring near-ideal capacitive behavior above typical MLCC limits
• High-speed optical transceiver interposers (100G/400G/800G) where 0.15mm profile fits within hermetic TOSA/ROSA lid clearance
• Custom multi-capacitor array applications where wafer-level design flexibility enables single-chip solutions replacing multiple discrete components

OEM Customization and Assembly Quick Reference

Die Attach: AuSn eutectic solder (300-320°C, N2/H2) for lowest ground inductance. Conductive Ag epoxy (Epotek H20E, 120°C/30min) for low-temperature budget assembly.

Wire Bonding: 18µm or 25µm Au thermosonic ball bonding (120-150°C stage, >6gf pull strength). For SRF optimization, use dual parallel bonds or 25µm x 75µm Au ribbon.

Wafer-Level Customization: Contact our OEM team with your target capacitance, voltage, die geometry, metallization, and delivery format requirements. Prototypes ship in 3-4 weeks with full parametric test data and KGD wafer maps.

Storage: Waffle pack, gel-pak, or wafer-level per customer specification. MSL 1 unlimited floor life at 30°C/85%RH.

Contact us today to discuss your miniaturized high-density capacitor requirements. Standard 220pF 0.35mm evaluation samples ship within 2-3 weeks. Custom wafer-level designs with full OEM support available with 3-4 week prototyping lead time.