High-K Dielectric 330pF 25V MOS Capacitor Ultra-Low Phase Noise Wire Bondable

Product Specification

HACC331S25V500 Custom High-K Dielectric MOS Capacitor 330pF 25V Ultra-Low Phase Noise for VCO & PLL Circuits — Fully Customizable

The HACC331S25V500 is a fully customizable 330 pF 25 V single-layer MOS capacitor featuring an engineered high-K composite dielectric stack (SiO&sub2;/Al&sub2;O&sub3;/HfO&sub2;) that achieves 1,320 pF/mm² areal capacitance density—over 3× the density of conventional SiO&sub2;-only MOS capacitors—while delivering ultra-low phase noise below -165 dBc/Hz at 10 kHz offset for VCO tank circuits, PLL loop filters, and low-noise frequency synthesizers. Built on a fully configurable platform, this device is tailored to your capacitance (10 pF–1,000 pF), voltage (6.3 V–100 V), chip geometry, and metallization requirements with rapid prototyping turnaround.

High-K Dielectric for Superior Capacitance Density

The HACC331S25V500 overcomes the fundamental trade-off between capacitance density and RF performance through an engineered high-K dielectric stack deposited via atomic layer deposition (ALD) for Ångström-level thickness control. The complete stack (SiO&sub2; base + Al&sub2;O&sub3;/HfO&sub2; high-K layers) totals approximately 300 nm equivalent oxide thickness (EOT). At 330 pF in a standard 0.50 × 0.50 mm footprint, this device achieves 1,320 pF/mm²—more than 3× the areal capacitance density of conventional SiO&sub2;-only MOS capacitors and comparable to the best thin-film capacitor technologies.

Key design advantages of the high-K approach include:

• The SiO&sub2; base layer provides the atomically perfect silicon interface essential for low interface trap density (D_it <5×10¹⁰ cm⁻²eV⁻¹), ensuring minimal flicker noise contribution to VCO/PLL phase noise
• The Al&sub2;O&sub3; and HfO&sub2; high-K overlayers boost overall capacitance density through their higher dielectric constants (k≈9 for Al&sub2;O&sub3;, k≈25 for HfO&sub2;) while being physically separated from the silicon interface to avoid introducing additional trapping centers
• Pinhole-free ALD coverage across the entire capacitor area eliminates defect-driven leakage paths that degrade yield in sputtered or evaporated high-K films
• Zero internal electrodes and zero vias in the single-layer MOS architecture create a coaxial current path free of the parasitic inductance mechanisms that plague MLCCs

Ultra-Low Phase Noise for VCOs & PLLs

Phase noise in voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs) sets the fundamental limit on frequency synthesizer spectral purity. The HACC331S25V500 minimizes its contribution to VCO/PLL phase noise through three simultaneous design optimizations:

1. Ultra-Low 1/f Flicker Noise Through Trap-Minimized Dielectric Interface: The SiO&sub2; base layer, thermally grown on high-resistivity float-zone silicon (>1,000 Ω·cm), achieves an interface trap density below 5×10¹⁰ cm⁻²eV⁻¹—an order of magnitude improvement over deposited dielectrics. Combined with post-oxidation nitrogen annealing, the dielectric stack achieves a flicker noise corner frequency below 1 kHz.

2. Verified Phase Noise Performance in VCO Tank Circuits: When characterized as the resonator capacitor in a 10 GHz cross-coupled LC-VCO, the HACC331S25V500 contributes phase noise below -165 dBc/Hz at 10 kHz offset and below -185 dBc/Hz at 1 MHz offset. This performance is verified through residual phase noise measurement per IEEE Std 1139 using a two-oscillator cross-correlation technique.

3. High-K Dielectric Noise Optimization: High-K dielectrics are known to exhibit higher 1/f noise than SiO&sub2;. The HACC331S25V500 mitigates this through a thin SiO&sub2; interfacial layer that physically separates the silicon channel from the high-K layers—the trapping centers in Al&sub2;O&sub3; and HfO&sub2; are too far from the silicon interface to efficiently exchange carriers at low frequencies.

Key Electrical Specifications

• Capacitance: 330 pF ±10% (±5% optional), measured at 1 MHz, 1.0 Vrms, 25°C
• Rated DC Voltage: 25 V continuous
• Dielectric Withstanding Voltage: >75 V (300% rated), 5 sec dwell, 100% production tested
• Dielectric Type: High-K Composite (SiO&sub2;/Al&sub2;O&sub3;/HfO&sub2;), ALD deposited, ~300 nm EOT
• Capacitance Density: 1,320 pF/mm² (3× conventional SiO&sub2; MOS)
• Phase Noise @ 10 kHz Offset: < -165 dBc/Hz (10 GHz VCO, cross-correlation per IEEE Std 1139)
• 1/f Noise Corner Frequency: < 1 kHz (flicker noise plateau)
• Q Factor @ 1 MHz / @ 1 GHz: >1,500 / >150
• ESR @ 1 GHz: <0.12 Ω
• Intrinsic Chip ESL: <0.05 nH
• Dissipation Factor: ≤0.15% @ 1 kHz, 1.0 Vrms
• Temperature Coefficient of Capacitance (TCC): +35 ppm/°C (-55°C to +125°C)
• Operating Temperature Range: -55°C to +125°C
• Insulation Resistance: ≥10⁴ MΩ @ Rated Voltage DC, 25°C
• Dielectric Absorption: <0.1% @ 1 kHz
• Moisture Sensitivity: MSL 1 (Unlimited floor life per J-STD-020)
• Storage Temperature: -65°C to +150°C
• ESD Rating: Class 0 (HBM) per JESD22-A114

Physical & Construction Specifications

• Chip Dimensions: 0.50 × 0.50 × 0.15 mm (±25 μm)
• Design Architecture: Double-Sided Bordered (Margin)
• Substrate: Float-Zone Si, >1,000 Ω·cm
• Top Metallization: TiW-Au, ≥2.5 μm Au (wire bond optimized)
• Backside Metallization: TiW-Pt-Au, ≥1.0 μm Au with Pt diffusion barrier
• Wire Bond Pull Strength: >6 gf for 25 μm Au wire (MIL-STD-883 Method 2011.7)
• Chip-Level SRF: >2 GHz (no bond wire, de-embedded)
• System SRF (0.5 mm bond wire): >500 MHz (single 25 μm Au wire)
• Mounting Type: Wire Bondable / Conductive Epoxy or AuSn Eutectic Die Attach
• Compliance: RoHS Compliant (EU 2015/863), Halogen-Free per IEC 61249-2-21, REACH SVHC Free

Customization Platform — Design to Your Specification

The HACC331S25V500 is built on a fully configurable MOS capacitor platform. As a custom manufacturer, we offer full tailoring of the following parameters with 3–4 week prototyping turnaround:

• Capacitance: 10 pF to 1,000 pF; ±5% or tighter tolerance available
• Rated Voltage: 6.3 V DC to 100 V DC
• Dielectric Stack: Custom high-K materials (Al&sub2;O&sub3;, HfO&sub2;, ZrO&sub2;, Ta&sub2;O&sub5;); layer thickness ratios tailored to your capacitance density target
• Chip Dimensions: 0.25 × 0.25 mm to 5.0 × 5.0 mm; rectangular aspect ratios up to 4:1; irregular geometries on request
• Top Metallization: Up to 5.0 μm Au; Al-metallized; AuSn pre-deposition
• Backside Metallization: Au-only; AuSn/AuGe/AuSi pre-deposition for high-temperature attach
• Design Architecture: Single-Sided Bordered or borderless configurations available
• Prototype Lead Time: 3–4 weeks standard; expedited 1–2 weeks for standard capacitance values