Custom High Breakdown Voltage Low Leakage 1000 pF MOS Capacitor Ultra Stable TCC

Product Specification

HACC102S80V750 Custom High Breakdown Voltage MOS Capacitor 1000pF 80V Ultra-Stable TCC Low Leakage Wire-Bondable Chip

The HACC102S80V750 is a high-reliability, fully customizable Single Layer MOS capacitor engineered for applications demanding High Breakdown Voltage, Ultra-Low Leakage Current, and Exceptional Capacitance Stability over Temperature and Voltage. Fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO₂ dielectric, this device delivers 1000pF ±10% capacitance at 80V DC continuous operating voltage in a compact 0.75*0.75*0.20mm chip-scale package. The Double-Sided Bordered (Margin) architecture ensures epoxy containment and wire bond alignment reference. The TiW-Au top electrode with minimum 2.5µm gold thickness provides superior wire bond reliability, while the TiW-Pt-Au backside with platinum (Pt) diffusion barrier enables universal die-attach compatibility with conductive epoxy, AuSn eutectic, and sintered-Ag processes. Available with full customization of capacitance value, voltage rating, chip geometry, dielectric type, and metallization stack to meet your exact RF circuit requirements.

Key Performance Advantages

1. High Breakdown Voltage & Ultra-Low Leakage Current

Dielectric breakdown is one of the most common field failure mechanisms in chip capacitors operating at elevated voltage. The HACC102S80V750 eliminates this risk through conservative design margins and high-quality thermal SiO₂ dielectric:

• Rated Voltage: 80V DC continuous — suitable for GaN power amplifier drain bias networks operating at 28-50V with substantial headroom for supply transients and load mismatch reflections
• Dielectric Withstanding Voltage (DWV): >200V DC (>2.5* rated) — 100% production tested on every die. Exceeds the 2* derating guideline recommended by industry reliability standards for high-reliability applications
• Leakage Current: <10nA at 25°C, <100nA at 125°C — exceptionally low even at maximum rated temperature. Measured at full 80V DC bias
• Uniform Field Distribution: Unlike MLCCs where internal electrode edges concentrate electric fields creating partial discharge risk, the MOS capacitor's planar metal-insulator-semiconductor structure provides uniform field distribution across the entire capacitor area
• Time-Dependent Dielectric Breakdown (TDDB): >10 years lifetime at 125°C and rated voltage — verified through accelerated life testing

For the circuit designer, this means reliable DC blocking and RF bypass without requiring series stacking of multiple lower-voltage capacitors — reducing component count, assembly complexity, and cumulative tolerance stack-up. The 2.5* voltage margin absorbs supply transients, load mismatch reflections, and DC bias shifts that would challenge lower-rated capacitors.

2. Exceptional Capacitance Stability Over Temperature & Voltage

Capacitance that drifts with temperature or DC bias creates cascading problems in precision RF circuits: VCO frequencies wander, matching networks detune, filter corner frequencies shift. The HACC102S80V750's Class I COG/NPO (C0G/NP0) paraelectric ceramic dielectric provides consistent stability:

• Temperature Coefficient (TCC): 0 ±30 ppm/°C across -55°C to +125°C — capacitance variation below ±0.3% across the entire 180°C temperature span. This is 50* more stable than Class II X7R (±15%) and 100* more stable than X5R (±15% over narrower range)
• DC Bias Voltage Coefficient (VCC): <10 ppm/V — near-zero capacitance shift from 0V to full 80V rated voltage. X7R/X5R dielectrics lose 30-80% of rated capacitance under DC bias due to ferroelectric domain clamping; COG/NPO is paraelectric and maintains consistent bypass impedance at all bias levels
• Zero Aging Effect: No ferroelectric domains — capacitance is stable for the life of the product. Class II capacitors degrade logarithmically (3-5% per decade-hour) as ferroelectric domains relax. A capacitor measured at 100nF after reflow may read 85nF after 10,000 hours — the HACC102S80V750 eliminates this drift mechanism entirely
• Low Dielectric Absorption: <0.1% — minimizes charge memory effects in sample-and-hold and precision integrator applications

For defense and aerospace systems with multi-decade service lives, COG/NPO's zero-aging characteristic eliminates a critical long-term capacitance drift mechanism that would otherwise require periodic recalibration or component replacement.

3. Wire-Bondable Top Contact with Multi-Layer Metallization

The top electrode features an advanced four-layer sputtered thin-film metallization stack — TaN/TiW/Ni/Au with minimum 2.5µm gold thickness — providing robust, high-yield wire bonding in automated assembly environments:

• TaN Adhesion Layer: Forms the strongest known oxide-blocking chemical bond to the ceramic dielectric, preventing electrode delamination under rapid thermal cycling (ΔT=180°C)
• TiW Diffusion Barrier: Dense amorphous barrier prevents silicon or substrate contaminant migration into the gold layer — eliminating brittle intermetallic formation at the bond interface
• Ni Anti-Leaching Layer: Completely insoluble in AuSn and lead-free solders — preserves bond integrity during high-temperature eutectic die attach reflow
• Au Bond Surface (≥2.5µm): Thick, ductile gold mechanically absorbs 40-100mW ultrasonic bonding energy, preventing bond-through/cratering failure modes. Bond pull strength >6gf for 25µm Au wire — exceeding MIL-STD-883 Method 2011.7

The 0.75*0.75mm footprint provides a generous wire bond pad area, accommodating multiple parallel bonds for reduced inductance in high-current applications. Compatible with 18-25µm Au thermosonic ball bonding and 25-33µm Al ultrasonic wedge bonding.

Customization Platform — Designed to Your Specification

The HACC102S80V750 is built on our configurable MOS capacitor platform. We offer full customization with rapid prototyping turnaround:

Technical Specifications

Typical Applications

• GaN-on-SiC HEMT Power Amplifier Drain Bias Decoupling (28-50V supply)
• High-Voltage DC-DC Converter Output Filtering
• RF Power Amplifier DC Blocking in Bias Tee Networks
• Pulsed Power Energy Storage & Bypass
• Phased-Array T/R Module High-Voltage Supply Decoupling
• Satellite Communication Bus Power Distribution (LEO/MEO/GEO)
• Industrial RF Plasma Generator Matching (13.56/27.12 MHz ISM bands)
• ATE Pin Electronics High-Voltage Decoupling
• Automotive Radar & V2X Modules (76-81GHz, AEC-Q200 compatible)

Assembly Quick Reference

• Die Attach: Conductive silver epoxy (Epotek H20E, 120°C/30min cure), AuSn eutectic solder (300-320°C, N₂/H₂ forming gas), or sintered-Ag for high-temperature applications. Bottom Pt barrier ensures universal compatibility
• Wire Bonding: 25µm Au thermosonic ball bonding (120-150°C stage, 15-35gf force, 40-80mW ultrasonic, >6gf pull strength) or 25µm Al ultrasonic wedge bonding at room temperature. Multiple parallel bonds for >1A RMS RF current
• Bond Clearance: Bond landing ≥25µm from electrode edge. Ceramic margin provides unambiguous optical reference for automated wire bonder vision systems
• Storage: Waffle pack or gel-pak in nitrogen cabinet at 20-25°C, 40-60% RH. MSL 1: unlimited floor life at ≤30°C/85%RH. 1-year guaranteed shelf life under optimal conditions

Contact us today with your voltage, capacitance, and geometry requirements. Standard 1000pF 80V evaluation samples ship within 1-2 weeks. Custom voltage ratings (up to 500V single-layer, 1000V stacked), capacitance values, chip dimensions, and metallization options available with 3-4 week prototyping lead time. Full RoHS, REACH, halogen-free compliance documentation, S-parameter data, and lot traceability reports provided per production lot.