| Capacitance Range | From a few pF to several nF |
| Structure | Metal-Oxide-Semiconductor |
| Oxide Material | Silicon dioxide (SiO2) or high-k dielectrics |
| Metal Gate Material | Aluminum, polysilicon, or metal alloys |
| Delivery Time | 7-10 working days space grade |
| Application | Used in semiconductor device characterization and memory devices |
| Frequency Response | Up to GHz range |
| Supply Ability | |
| Dielectric Constant | 3.9 for SiO2, higher for high-k materials |
| Payment Terms | L/C,D/A,D/P,T/T, |
| Oxide Thickness | Typically 5-100 nm |
| Brand Name | Hoan |
| Place of Origin | Shannxi,China |
| Model Number | HACC100S10V101 |
| Certification | ISO 9001:2015, RoHS, REACH, ESA ESCC |
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Product Specification
| Capacitance Range | From a few pF to several nF | Structure | Metal-Oxide-Semiconductor |
| Oxide Material | Silicon dioxide (SiO2) or high-k dielectrics | Metal Gate Material | Aluminum, polysilicon, or metal alloys |
| Delivery Time | 7-10 working days space grade | Application | Used in semiconductor device characterization and memory devices |
| Frequency Response | Up to GHz range | Supply Ability | |
| Dielectric Constant | 3.9 for SiO2, higher for high-k materials | Payment Terms | L/C,D/A,D/P,T/T, |
| Oxide Thickness | Typically 5-100 nm | Brand Name | Hoan |
| Place of Origin | Shannxi,China | Model Number | HACC100S10V101 |
| Certification | ISO 9001:2015, RoHS, REACH, ESA ESCC | ||
| High Light | Custom RF Chip Capacitor ,Radiation Hardened RF Chip Capacitor ,Radiation Hardened Space Capacitor | ||
The HACC101S10V500 is specifically designed and qualified for space environments where total ionizing dose (TID) radiation degrades standard MOS structures. The radiation-hardened gate oxide — using nitrided SiO₂ or hardened Al₂O₃ formulations — minimizes radiation-induced interface trap generation and fixed oxide charge accumulation, the two primary mechanisms that cause threshold voltage shift and capacitance drift in irradiated MOS devices.
Qualification per ESCC 22900 demonstrates TID hardness >100 krad(Si) for the standard formulation and >300 krad(Si) with hardened oxide, with inductance-capacitance shift maintained below 5% at maximum TID. Post-irradiation annealing stability is verified: <1% additional shift after 168 hours at 100°C. The MOS capacitor architecture is inherently immune to single event effects (SEE) — no latch-up path exists (it is a two-terminal passive device), no SEU-sensitive node is present, and single event gate rupture is prevented by the dielectric thickness. This SEE immunity is a fundamental architectural advantage over active semiconductor devices and is verified by design, not by sample testing.
Space-qualified RF subsystems require consistent impedance across frequency — and radiation must not degrade that consistency. The HACC101S10V500 delivers engineered flat-Q response with Q maintained within ±5% across the customer-specified band, and Q degradation verified <3% after 100 krad TID exposure. This ensures that your matching network, filter, or bias network performance remains stable from pre-launch verification through end-of-mission life.
Space-grade assembly requires full die-level traceability and automated sorting by electrical grade. The HACC101S10V500 delivers a complete digital wafer map in industry-standard XML KRF format, compatible with SECS-II fab automation and GDSII layout tools. Each die is binned by capacitance value, ESR, Q factor, and — uniquely for the RH variant — TID test grade from the wafer-level radiation qualification sample. The wafer map integrates directly with automated pick-and-place die sorters: die extraction by map bin code, full known-good-die (KGD) traceability per bin, and lot-level documentation suitable for ESA/NASA materials review board (MRB) submission.
| Parameter | Value |
|---|---|
| TID Hardness | >100 krad(Si) standard, >300 krad(Si) hardened, ESCC 22900 |
| SEE Immunity | Immune — no latch-up path, no SEU node, no gate rupture |
| Post-TID Q Degradation | <3% after 100 krad |
| Post-Irradiation Stability | <1% L shift after 168h 100°C anneal |
| Flat-Q Response | ±5% flatness, radiation-stable |
| Wafer Map Format | XML KRF, GDSII, SECS-II, binning by C/ESR/Q/TID |
| Capacitance | 5pF–10,000pF |
| Dielectric Type | Rad-hard nitrided SiO₂, Al₂O₃ hardened |
| Operating Temperature | -55°C to +125°C, full post-radiation parametric |
| Certification | ISO 9001:2015, ESA ESCC qualified, space-grade LAT |
Contact us with your TID requirement, mission profile, and wafer map format preference. ESA ESCC qualified radiation-hardened MOS capacitor prototypes with digital wafer map ship in 7–10 business days.
Company Details
Business Type:
Manufacturer
Year Established:
50%-60%
Total Annual:
>1000000
Employee Number:
>100
Ecer Certification:
Verified Supplier
Xi'an Hoan Microwave Co., Ltd. was established in 2005. The company is located in the High-tech Zone of Xi'an. The company covers an area of 800 square meters, including 500 square meters of production area and 300 square meters of office area. It is a professional enterprise specializing in t... Xi'an Hoan Microwave Co., Ltd. was established in 2005. The company is located in the High-tech Zone of Xi'an. The company covers an area of 800 square meters, including 500 square meters of production area and 300 square meters of office area. It is a professional enterprise specializing in t...
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