Flat Q Response Low ESR Capacitor Ultra Low Dielectric Absorption Eutectic

Product Specification

Custom MOS Capacitor Eutectic Backside Metallization Flat Q Response Ultra Low Dielectric Absorption

HACC-CUSTOM-BM: Eutectic-Optimized MOS Capacitor with Flat-Q Response & Ultra-Low Dielectric Absorption

Customized Backside Metallization for Eutectic Soldering

The HACC-CUSTOM-BM offers customer-selectable backside metallization stacks optimized for eutectic die attach processes. Three gold-based eutectic alloy systems are available, selected based on your assembly thermal budget and reliability requirements:

• AuSn (80Au/20Sn): Eutectic temperature 280°C. Industry standard for high-reliability hybrid circuits. TiW-Ni-Au backside with 3-15µm AuSn pre-form. Die shear strength >2.5 kg/mm² on gold pad.
• AuGe (88Au/12Ge): Eutectic temperature 356°C. Higher thermal budget for subsequent reflow processes. Low oxidation rate during storage.
• AuSi (97Au/3Si): Eutectic temperature 363°C. Maximum thermal headroom for multi-step assembly flows. Preferred for silicon-on-silicon attach where CTE matching is critical.

All backside stacks include a TiW diffusion barrier (2000Å) to prevent gold-silicon interdiffusion, and a Ni barrier layer (500-2000Å) for AuSn soldering to prevent Sn consumption by the Au layer. Solder wettability exceeds 95% area coverage with X-ray voiding verified below 5% — ensuring uniform thermal and electrical conductivity across the entire die attach interface.

Engineered Flat-Q Frequency Response

Standard MOS capacitors exhibit Q factor that varies significantly with frequency — typically peaking at a few hundred MHz then rolling off. For broadband RF applications (matching networks, bias tees, filter resonators), this Q(f) variation complicates design and limits usable bandwidth. The HACC-CUSTOM-BM offers engineered flat-Q response: Q maintained flat within ±5% across a customer-specified band from 100MHz to 10GHz, with Q roll-off controlled to <10% per decade beyond the plateau. This is achieved through tailored substrate doping (controlling series resistance frequency dependence) and electrode geometry optimization (controlling skin effect and current crowding). The result is a capacitor whose Q is predictable across your entire operating band — no Q peaks, no Q cliffs, and no surprises during prototype testing.

Ultra-Low Dielectric Absorption & Zero Charge Storage

Dielectric absorption (DA) — the "memory effect" where a capacitor retains residual charge after discharge — is a critical parameter for sample-and-hold circuits, precision integrators, and charge-sensitive amplifiers where held charge must accurately represent the sampled voltage. The thermally grown SiO₂ dielectric in HACC-CUSTOM-BM achieves DA <0.05% at 1kHz and <0.02% at 1MHz — among the lowest of any capacitor technology. Combined with zero piezoelectric output (no mechanical-to-electrical coupling, unlike MLCCs with barium titanate dielectrics) and zero microphonic sensitivity, the HACC-CUSTOM-BM is ideal for precision analog applications where charge integrity is paramount.

Key Specifications

Applications

• Hybrid Circuit Eutectic Assembly Lines — AuSn/AuGe/AuSi backside selection per process thermal budget
• Broadband RF Matching Networks — flat-Q response for consistent impedance across multi-octave bands
• Precision Sample-and-Hold Circuits — DA <0.05% for charge integrity, zero piezoelectric output
• Charge-Sensitive Preamplifiers — near-zero dielectric absorption eliminates memory effect errors

Contact us with your eutectic alloy preference, target Q profile, and dielectric absorption requirements. Custom backside metallization MOS capacitor prototypes ship in 5–7 business days.