Extreme Voltage Dielectric Single Layer Ceramic Capacitor Wafer Level High

Product Specification

Custom MOS Capacitor Dielectric Thickness Extreme Voltage Wafer Level Gel Pak Delivery Doping Resistivity Control

HACC-CUSTOM-DV: Extreme-Voltage MOS Capacitor with Flexible Wafer-Level & Gel-Pak Delivery

Customized Dielectric Thickness for Extreme Voltages

The HACC-CUSTOM-DV extends the single-layer MOS capacitor voltage range through engineered dielectric thickness. The standard thermally grown SiO₂ dielectric (50–5000Å) supports rated voltages up to 500V. For higher voltage requirements, a stacked dielectric architecture — combining SiO₂ with stress-controlled SiN or high-k Al₂O₃ layers — achieves rated voltages up to 1000V while maintaining capacitance density. Dielectric withstanding voltage (DWV) is verified at 250–300% of rated voltage on every wafer, and time-dependent dielectric breakdown (TDDB) lifetime exceeds 10 years at maximum rated temperature. Thickness tolerance is ±2% wafer-level and ±1% within-die, verified by spectroscopic ellipsometry on every wafer.

The air-free single-layer MOS architecture eliminates the delamination and partial discharge risks associated with multi-layer ceramic capacitors (MLCCs) at high voltage gradients. Unlike MLCCs where internal electrode edges concentrate electric fields, the MOS capacitor's planar metal-insulator-semiconductor structure provides uniform field distribution across the entire capacitor area — a critical advantage for high-voltage reliability.

Flexible Wafer-Level, Waffle Pack, or Gel-Pak Delivery

The HACC-CUSTOM-DV accommodates any downstream assembly flow with three delivery options, individually selectable per production lot or mixed per wafer split:

• Wafer-Level: Full wafer delivery — probed, inked, and mapped with known-good-die binning. Options include sawn wafer on frame (for direct pick-and-place) or expanded film frame for die sorting.
• Gel-Pak: Sawn die placed on Gel-Pak trays with vacuum release for clean pick-and-place. Class 100 cleanroom packed, ideal for automated hybrid circuit assembly lines.
• Waffle Pack: Sawn die in anti-static waffle packs, vacuum-sealed with nitrogen purge. Includes known-good-die (KGD) map for die-level traceability.

Mixed packaging — for example, 50% of a wafer as Gel-Pak and 50% as waffle pack — is supported without requalification, providing maximum flexibility for prototype-to-production transitions or multi-site assembly flows.

Tailored Substrate Doping & Resistivity Control

As with all HACC-CUSTOM products, substrate doping is a design parameter: N+ or P+ profiles with resistivity from 0.001 to 1000 Ohm·cm, optimized for the target breakdown voltage (BVdss) and series resistance trade-off. The C-V characteristic can be shaped for flat capacitance or controlled-slope varactor behavior.

Key Specifications

Applications

• High-Voltage DC-DC Converter Filtering — 500V rated single-layer MOS capacitors replace MLCC banks
• Pulsed Power Energy Storage — stacked dielectric for 1000V operation, uniform field distribution
• High-Voltage Bias Networks — wafer-level delivery for automated hybrid circuit assembly
• ATE Pin Electronics Decoupling — Gel-Pak delivery for clean pick-and-place, Class 100 cleanroom

Contact us with your voltage requirement, dielectric specifications, and delivery format preference. Extreme-voltage MOS capacitor prototypes ship in 5–7 business days.