Near Zero Inductance MOS Capacitors Single Layer 30V 100 pF Capacitor Chip For

Product Specification

Near-Zero Inductance MOS Capacitor HACC101S30V101 100pF 30V Single Layer Chip for Broadband RF Microwave Circuits

HACC101S30V101 Single-Layer MOS Capacitor: Low-Inductance, Microphonic-Free 100pF for GHz Circuits

The HACC101S30V101 is a 100pF ±10% single-layer MOS capacitor rated at 30V DC, built on a float-zone silicon substrate (>1000Ω·cm) with 300nm thermal SiO₂ dielectric. Chip dimensions are 0.50mm * 0.50mm * 0.15mm with 2.5µm minimum gold top metallization and 1.0µm minimum gold backside. It is optimized for applications above 1GHz where parasitic series inductance, vibration-induced noise, and capacitance unit-to-unit spread directly determine system-level performance.

1. How Single-Layer Construction Achieves Sub-0.05nH ESL

Equivalent series inductance (ESL) in a capacitor arises from the magnetic flux enclosed by the current loop through the device. In a multilayer ceramic capacitor (MLCC), each internal electrode pair forms a current loop, and the stack of N electrode pairs creates N parallel loops whose mutual inductance adds constructively. The result is ESL that scales poorly with both layer count and chip length.

The single-layer MOS structure eliminates this mechanism:

• Vertical-only current path: Current flows from the top gold electrode, vertically through the SiO₂ dielectric, into the silicon substrate, and out through the backside gold—a single loop with minimal enclosed area. There is no horizontal current flow along internal electrodes.
• Dielectric thickness vs. inductance: The 300nm SiO₂ layer defines the current path length through the dielectric. At this scale, the magnetic flux contribution from the dielectric region is dominated by the bond wire and external circuit geometry.
• Measured ESL values: For a 0.50mm chip with a single 25µm diameter, 0.5mm-long gold bond wire, the total loop inductance is approximately 0.4nH. Subtracting the bond wire contribution (~0.35nH for 0.5mm of 25µm Au wire) leaves an intrinsic chip ESL below 0.05nH. With multiple parallel bond wires, the effective ESL scales roughly as 1/N.
• Practical consequence: At 100pF, the series resonance with 0.05nH ESL occurs above 2.2GHz—but the intrinsic chip ESL is low enough that the user-controlled bond wire inductance dominates, giving the circuit designer direct control over the resonant frequency through bond wire length selection.

2. Material Basis for Zero Piezoelectric Response

The microphonic effect in capacitors occurs when mechanical strain induces a voltage through either the direct piezoelectric effect (strain → polarization) or through dimensional changes in the dielectric (strain → capacitance modulation). Both mechanisms depend on the dielectric material's crystallographic structure.

Thermally grown SiO₂ is free of both effects:

• Amorphous structure: Unlike crystalline quartz (which is piezoelectric) or ferroelectric BaTiO₃ (which is both piezoelectric and electrostrictive), amorphous SiO₂ lacks long-range crystallographic order. Piezoelectricity requires a non-centrosymmetric crystal structure—a condition the random atomic network of amorphous silica cannot satisfy.
• No ferroelectric domains: Barium titanate (BaTiO₃) in X7R and X5R capacitors derives its high dielectric constant from domain wall motion—the reorientation of Ti⁴⁺ ions within the perovskite unit cell under applied electric field. This mechanism is inherently nonlinear, hysteretic, and mechanically coupled. SiO₂ has a dielectric constant of approximately 3.9 with no ferroelectric component, yielding a perfectly linear C-V characteristic from 0V to rated voltage.
• Electrostriction comparison: All dielectrics exhibit some electrostriction (strain proportional to the square of the electric field), but the effect in SiO₂ is orders of magnitude smaller than in high-K ferroelectrics. The electrostrictive coefficient of thermal SiO₂ is below 10^-22 m²/V², compared to approximately 10^-16 m²/V² for BaTiO₃—a factor of one million difference.

3. Wafer-Level Process Control for Capacitance Uniformity

Capacitance value consistency across a production lot depends on two factors: dielectric thickness uniformity and electrode area definition. The HACC fabrication sequence addresses both:

• Dry thermal oxidation: Silicon wafers are oxidized in a quartz furnace at 950-1050°C in a dry O₂ ambient. The Deal-Grove oxidation kinetics produce self-limiting growth, where the oxide thickness variance across a 150mm wafer is typically under ±2% (measured by spectroscopic ellipsometry at 49 points per wafer).
• Electrode lithography: The top gold electrode is defined by a lift-off process using contact photolithography. Electrode area variation is controlled by the lithography mask critical dimension (CD) tolerance of ±1µm on a nominal 400µm electrode dimension, contributing under ±0.5% to capacitance variation.
• 100% wafer-level DC test: Every capacitor site on every wafer is probed for capacitance at 1MHz, leakage current at rated voltage, and breakdown voltage. Sites exceeding specification limits are inked for exclusion at dicing. Lot acceptance is based on a minimum 95% probe yield.
• TiW adhesion and barrier layer: A thin TiW (titanium-tungsten, typically 100nm) layer is deposited between the silicon/SiO₂ surface and the gold electrode. This layer serves three functions: adhesion promotion (preventing gold delamination during wire bonding), diffusion barrier (blocking silicon-gold interdiffusion at elevated temperatures), and current spreading (reducing localized current density at bond sites).

4. RF Performance Characteristics

Small-signal S-parameter measurements (1-20GHz, GSG probe, short-open-load-thru calibration) on the HACC101S30V101 yield the following typical performance:

• Q factor: >2000 at 1MHz, >300 at 1GHz, >80 at 5GHz. The Q roll-off with frequency follows the expected 1/(ωCR_s) trend, where R_s includes both ESR and substrate-induced losses. The high-resistivity float-zone substrate (>1000Ω·cm) minimizes eddy current losses that would otherwise degrade Q in standard Czochralski silicon substrates.
• Insertion loss: Series-connected (two-port) insertion loss is below 0.1dB through 6GHz for a 50Ω system, making the capacitor suitable for low-loss matching and DC-blocking applications.
• Series resonance: With a 0.5mm bond wire, the total inductance of ~0.4nH produces a series self-resonance at approximately 800MHz for the 100pF value. This is well-characterized and can be shifted by adjusting bond wire geometry—a degree of freedom not available with discrete packaged capacitors.

Key Features

• Near-Zero Intrinsic Inductance: Chip ESL below 0.05nH. System inductance dominated by user-controlled bond wire, providing tunable self-resonance.
• Zero Piezoelectric Output: Amorphous SiO₂ dielectric with no piezoelectric coefficient. Zero singing capacitor effect and zero microphonic noise pickup, verified by vibration testing per MIL-STD-202 Method 204 (no measurable output above noise floor at 10g peak acceleration, 20Hz-2kHz sweep).
• High Capacitance Uniformity: ±2% oxide thickness uniformity combined with ±1µm electrode CD control. ±10% standard tolerance, ±5% available. No DC bias capacitance derating.
• TiW-Au Metallization System: 100nm TiW barrier/adhesion layer + 2.5µm minimum gold top electrode. Bond pull strength >6gf for 25µm Au wire. Backside: TiW-Pt-Au with Pt barrier for silver epoxy compatibility.
• High-Resistivity Substrate: Float-zone silicon with >1000Ω·cm resistivity minimizes substrate RF losses, enabling Q > 300 at 1GHz.

Electrical Specifications (T = 25°C unless noted)

Application Design Guidance

VCO and PLL Circuits: The absence of piezoelectric response makes the HACC101S30V101 suitable for oscillator tank circuits where mechanical vibration would otherwise modulate the capacitance and appear as phase noise sidebands. In a typical 2GHz VCO with a 100pF tank capacitor, a piezoelectric sensitivity of 1ppm/g (typical for X7R) produces a vibration-induced frequency modulation of 2kHz/g. The HACC101S30V101 eliminates this mechanism at the component level.

Broadband Bypass: For supply decoupling above 1GHz, mount the chip as close to the active device as practical. A 0.5mm bond wire from the capacitor top electrode to the device pad produces a series resonant frequency near 800MHz with the 100pF value. Above this frequency, the capacitor appears inductive—but the inductance value is the well-controlled bond wire inductance, not an unknown internal ESL. For bypass covering 1-6GHz, use two parallel bond wires to halve the effective inductance and double the series resonant frequency.

LNA Matching: The Q > 300 at 1GHz ensures that the capacitor contributes negligible loss to input matching networks. When designing an L-section match, the inductor—not the capacitor—will dominate network loss. Use the capacitor as the series element (DC block) or shunt element, depending on the impedance transformation ratio.

Assembly

Die attach: eutectic AuSn (320°C peak, N₂/H₂ atmosphere) or conductive Ag epoxy. Wire bond: 25µm Au thermosonic ball bonding (120-150°C stage, 25-35gf bond force, >6gf pull strength) or 25µm Al ultrasonic wedge bonding at room temperature. ESD Class 0 (HBM).

Contact us for measured S-parameter data, wafer-level C-V maps, vibration test reports, or custom capacitance values on the 0.50mm platform.