Beijing Silk Road Enterprise Management Services Co., Ltd.
| Operating Temperature | -40℃~+125℃ |
| Output Frequency(Max) | 100MHz |
| Number of Outputs | 2 |
| Voltage - Supply | 1.71V~3.63V |
| Description | 100MHz 2 VFLGA-6 Pin Configurable/Selectable Oscillators RoHS |
| Mfr. Part # | DSC612RI3A-010J |
| Package | VFLGA-6 |
| Model Number | DSC612RI3A-010J |
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Product Specification
| Operating Temperature | -40℃~+125℃ | Output Frequency(Max) | 100MHz |
| Number of Outputs | 2 | Voltage - Supply | 1.71V~3.63V |
| Description | 100MHz 2 VFLGA-6 Pin Configurable/Selectable Oscillators RoHS | Mfr. Part # | DSC612RI3A-010J |
| Package | VFLGA-6 | Model Number | DSC612RI3A-010J |
The DSC612 is a MEMS low power, ultra-small footprint, crystal-less family of clock generators. It eliminates the need for an external crystal or reference clock, offering enhanced reliability and accelerated product development. The DSC612 generates up to two independent LVCMOS output clocks, each configurable from 2 kHz to 100 MHz, with options for output enable/disable, standby, sleep, spread spectrum enable, and frequency select.
| Parameter | Symbol | Min. | Typ. | Max. | Units | Conditions |
| Supply Voltage | VDD | 1.71 | 3.63 | V | Note 1 | |
| Active Supply Current | IDD | 5 | 6 | mA | fCLK1 = 27 MHz, fCLK2 = 25 MHz, VDD = 1.8V, No Load | |
| Active Supply Current (Sleep Mode, 1 PLL Off) | IDDSL | 3 | mA | CLK2 = SLEEP, fCLK1 = 25 MHz, VDD = 1.8V, No Load | ||
| Active Supply Current (32.768 kHz Output Only) | IDD32k | 1.4 | mA | CLK2 = SLEEP, fCLK1 = 32.768 kHz, VDD = 1.8V, No Load | ||
| Standby Supply Current | ISTDBY | 1.0 | A | VDD = 1.8V/2.5V | ||
| Standby Supply Current | ISTDBY | 1.5 | A | VDD = 3.3V | ||
| Frequency Stability | f | 20 | ppm | All temperature ranges | ||
| Frequency Stability | f | 25 | ppm | All temperature ranges | ||
| Frequency Stability | f | 50 | ppm | All temperature ranges | ||
| Aging | f | 5 | ppm | 1st year @ +25C | ||
| Aging | f | 1 | Per year after the first year | |||
| Startup Time | tSU | 1.5 | ms | From 90% VDD to valid clock output, T = +25C | ||
| Input Logic High | VIH | 0.7 x VDD | V | Input waveform must be monotonic with rise/fall time < 10 ms. | ||
| Input Logic Low | VIL | 0.3 x VDD | V | Input waveform must be monotonic with rise/fall time < 10 ms. | ||
| Output Disable Time | tDA | 200 + 2 Periods | ns | Note 5 | ||
| Output Enable Time | tEN | 1.0 | s | For parts configured with OE, not Standby. | ||
| Output Logic High | VOHY | 0.8 x VDD | V | I = 6 mA (high drive) or I = 3 mA (standard drive) | ||
| Output Logic Low | VOLY | 0.2 x VDD | I = 6 mA (high drive) or I = 3 mA (standard drive) | |||
| Output Transition Time, Rise Time/Fall Time (Standard drive) | tRY1/tFY1 | 1.2 | 2.0 | ns | CL = 10 pF, VDD = 1.8V | |
| Output Transition Time, Rise Time/Fall Time (Standard drive) | tRY1/tFY1 | 0.6 | 1.2 | ns | CL = 10 pF, VDD = 2.5V/3.3V | |
| Output Transition Time, Rise Time/Fall Time (High drive) | tRY2/tFY2 | 1.0 | 1.5 | ns | CL = 15 pF, VDD = 1.8V | |
| Output Transition Time, Rise Time/Fall Time (High drive) | tRY2/tFY2 | 0.5 | 1.0 | ns | CL = 15 pF, VDD = 2.5V/3.3V | |
| Frequency | f0 | 0.002 | 100 | MHz | ||
| Output Duty Cycle | SYM | 45 | 55 | % | ||
| Period Jitter, RMS | JPER | 17 | ps | fCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 1.8V | ||
| Period Jitter, RMS | JPER | 14 | ps | fCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 3.3V | ||
| Period Jitter, RMS | JPER | 9 | ps | fCLK1 = 27 MHz, fCLK2 = 27 MHz or 32.768 kHz, VDD = 3.3V | ||
| Period Jitter, Peak-to-Peak | JPER | 120 | ps | fCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 1.8V | ||
| Period Jitter, Peak-to-Peak | JPER | 100 | ps | fCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 3.3V | ||
| Period Jitter, Peak-to-Peak | JPER | 80 | ps | fCLK1 = 27 MHz, fCLK2 = 27 MHz or 32.768 kHz, VDD = 3.3V | ||
| Cycle-to-Cycle Jitter (peak) | JCy-Cy | 105 | ps | fCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 1.8V | ||
| Cycle-to-Cycle Jitter (peak) | JCy-Cy | 90 | ps | fCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 3.3V | ||
| Cycle-to-Cycle Jitter (peak) | JCy-Cy | 70 | ps | fCLK1 = 27 MHz, fCLK2 = 27 MHz or 32.768 kHz, VDD = 3.3V | ||
| Junction Operating Temperature | TJ | +150 | C | |||
| Storage Temperature Range | TS | 55 | +150 | C | ||
| Lead Temperature | +260 | C | Soldering, 40s |
Company Details
Business Type:
Manufacturer,Distributor/Wholesaler,Agent,Importer
Year Established:
2009
Employee Number:
>>300
Ecer Certification：
Verified Supplier
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