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The OptiMOS3 Power MOS Transistor Chip IPC300N20N3 is an N-channel enhancement mode bare die designed for industrial and multimarket applications. It features a drain-source breakdown voltage of 200V and a typical on-resistance of 9.2 m. This bare die is suitable for applications requiring high performance and reliability, with options for die bonding via soldering or gluing. It is manufactured with advanced passivation and metallization systems for robust performance.
Product Attributes
Brand: OptiMOS3
Type: Power MOS Transistor Chip
Channel Type: N-channel enhancement mode
Package: Sawn on foil
Backside Metallization: NiV system
Frontside Metallization: AlSiCu system
Passivation: Nitride + Imide (on edge structure only)
Electrostatic Discharge Sensitive Device: According to MIL-STD 883C
Visual Inspection: AQL 0.65 (according to failure catalogue)
Technical Specifications
Parameter
Symbol
Unit
Value (Min.)
Value (Typ.)
Value (Max.)
Note / Test Condition
Drain-source breakdown voltage
V(BR)DSS
V
200
-
-
VGS=0 V, ID=1 mA
Gate threshold voltage
VGS(th)
V
2
3
4
VDS=VGS, ID=270 A
Zero gate voltage drain current
IDSS
A
-
0.1
1
VGS=0 V, VDS=160 V
Gate-source leakage current
IGSS
nA
-
1
100
VGS=20 V, VDS=0 V
Drain-source on-resistance
RDS(on)
m
-
9.2 2)
100 3)
VGS=10 V, ID=2.0 A
Reverse diode forward on-voltage
VSD
V
-
1.0
1.2
VGS=0 V, IF=1A
Avalanche energy, single pulse
EAS
mJ
-
40 4)
-
ID =30 A, RGS =25
Die size
-
mm
-
6 x 5
-
-
Thickness
-
m
-
250
-
-
1) Packaged in a P-TO220-3 (see ref. product)
2) Typical bare die RDS(on); VGS=10 V
3) Limited by wafer test-equipment
4) Wafer tested. For general avalanche capability refer to the datasheet of IPP110N20N3 G