Shenzhen Jiaqing Circuit Co., Ltd.
| Payment Terms | L/C,D/A,D/P,T/T |
| Line/Space Capability | 10/10 μm to 30/30 μm (SAP/MSAP) |
| Delivery Time | 15-30 Days |
| Glass Transition Temperature | 180°C – 225°C (DSC) |
| Layer Count | 2 – 12 layers |
| Via Diameter | 50 – 100 μm |
| Surface Finish | ENIG, ENEPIG, OSP |
| Core Thickness | 40 – 200 μm |
| Material | BT (Bismaleimide Triazine) resin |
| Brand Name | Jiaqing Circuit |
| Place of Origin | China |
| Certification | ISO9001 |
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Product Specification
| Payment Terms | L/C,D/A,D/P,T/T | Line/Space Capability | 10/10 μm to 30/30 μm (SAP/MSAP) |
| Delivery Time | 15-30 Days | Glass Transition Temperature | 180°C – 225°C (DSC) |
| Layer Count | 2 – 12 layers | Via Diameter | 50 – 100 μm |
| Surface Finish | ENIG, ENEPIG, OSP | Core Thickness | 40 – 200 μm |
| Material | BT (Bismaleimide Triazine) resin | Brand Name | Jiaqing Circuit |
| Place of Origin | China | Certification | ISO9001 |
Coreless ETS (Embedded Trace Substrate) BT IC substrate eliminates the thick glass-cloth reinforced core to achieve ultra-thin profiles (as thin as 0.13 mm for 2-6 layer structures) and superior warpage control. By embedding the outermost circuit pattern directly into the BT insulating material, ETS technology enables fine line/space down to 12/12 μm (sample) and 12/18 μm (mSAP production). The coreless construction reduces overall package height for FC-CSP applications (3*3 mm to 19*19 mm) with bump pitches ≥0.15 mm. Available in 2-8 layer configurations, these substrates are ideal for ultra-thin mobile devices, wearable electronics, and high-density SiP modules where thickness and warpage are critical constraints.
Coreless construction (as thin as 0.13 mm) enables thinner smartphones, tablets, and wearables without sacrificing interconnect density.
The ultra-thin profile and reduced warpage make ETS BT substrates ideal for smartwatches, hearables, and health monitoring devices.
Coreless technology supports multi-chip integration in compact form factors, essential for RF front-end modules and sensor hubs.
Fine line/space (12/18 μm) and bump pitch ≥0.15 mm enable high I/O count in compact package sizes (3*3 mm to 19*19 mm).
The coreless structure significantly reduces package warpage compared to conventional substrates, critical for large-die flip-chip assemblies and assembly yield optimization.
Company Details
Business Type:
Manufacturer
Year Established:
2012
Total Annual:
20000000-50000000
Employee Number:
201~300
Ecer Certification：
Verified Supplier
Jiaqing Circuit was founded in 2012 in Shenzhen, China. We own a 5,000 square meter manufacturing plant with a monthly PCB production capacity of 20,000 square meters, capable of manufacturing 2-48 layer PCBs. We deliver one-stop solutions including PCB design, PCB fabrication, BOM component sourcin... Jiaqing Circuit was founded in 2012 in Shenzhen, China. We own a 5,000 square meter manufacturing plant with a monthly PCB production capacity of 20,000 square meters, capable of manufacturing 2-48 layer PCBs. We deliver one-stop solutions including PCB design, PCB fabrication, BOM component sourcin...
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