1000pF 35V MOS Capacitor SiO2 Dielectric Gold Metal Low ESR Capacitor For RF IC

Product Specification

HACC102S35V500 1000pF 35V MOS Capacitor High Q Low ESR Gold Metal Low ESR Capacitor For RF IC

HACC102S35V500: Foundry-Integrated 1000pF 35V MIM Capacitor for Low-Loss RF Signal Paths

Product Positioning

The HACC102S35V500 is purpose-built for RF design engineers who cannot afford insertion loss. Every parameter — from the 2.5μm gold top metal to the thermally-grown SiO2 dielectric — has been optimized for one goal: maximum Q factor with minimum ESR in a die that drops directly into your existing foundry flow.
Unlike discrete SMD capacitors that introduce 200-500pH of parasitic inductance at the board level, the HACC102S35V500 integrates at the die or module level, reducing interconnect parasitics by an order of magnitude. For a 5G n77 power amplifier output match, that difference can mean 2-3 percentage points of PAE.

Why Q Factor Matters in Your Design

In an RF matching network, the loaded Q of the inductor typically limits bandwidth. But capacitor Q determines insertion loss. At 3.5GHz — the heart of 5G sub-6GHz — the HACC102S35V500 maintains a Q exceeding 100. In a two-element L-match with a Q=40 inductor, switching from a Q=50 capacitor (typical MLCC) to a Q=100+ capacitor (HACC102S35V500) recovers approximately 0.4dB of through-loss. In a 4-stage Doherty PA with 8 matching elements, the cumulative improvement exceeds 2dB — the difference between meeting and missing 3GPP ACLR masks.

Foundry Integration: No Process Changes Required

The HACC102S35V500 is manufactured on a standard high-resistivity silicon substrate (>1000 Ω·cm) using only materials and processes available in every major CMOS and BiCMOS fab:

• Thermally-grown SiO2 — the same gate oxidation furnace used for transistor gate dielectrics
• Sputtered gold metallization — standard back-end-of-line metal deposition
• PECVD Si3N4 passivation — standard interconnect dielectric

No exotic materials. No specialized equipment. No process qualification hurdle. The HACC series Process Design Kit (PDK) includes DRC rules, layer mapping, and verified device models calibrated to 40GHz — ready for direct import into Cadence Virtuoso, Keysight ADS, or ANSYS HFSS.

Performance Benchmarks

Target Application Deep-Dive

5G NR Power Amplifier Output Matching

Modern 5G handsets pack up to 12 PA cores across n77/n78/n79 bands. Output matching networks operate at 3.3-5.0GHz where every milliohm of ESR directly subtracts from radiated power. The HACC102S35V500's sub-0.3Ω ESR at 1MHz (sub-0.5Ω at 1GHz) minimizes matching network loss, while the 35V rating accommodates the >10V peak voltages seen in envelope-tracking PA supply modulators.

Phased-Array Beamformer Front-Ends

SATCOM and radar phased arrays require channel-to-channel gain and phase matching across hundreds of elements. With wafer-level σ<2% capacitance uniformity, the HACC102S35V500 ensures consistent impedance transformation across every beamformer channel, minimizing the calibration burden in digital beamforming architectures.

Microwave Point-to-Point Backhaul

E-band (71-86GHz) backhaul links demand capacitors with self-resonance well above the operating band. The HACC102S35V500's <50pH ESL pushes SRF beyond 20GHz, providing clean, resonance-free bypass and coupling through Ku, K, and Ka bands. For E-band operation, flip-chip mounting reduces effective ESL below 30pH.

Assembly Guidelines

Wire Bonding

Die Attach

• Conductive epoxy: Standard Ag-filled epoxy, cure per manufacturer recommendation. Compatible with Au backside metallization option.
• AuSn eutectic: 80Au/20Sn preform at 300-320°C under forming gas. Lowest thermal resistance for high-power applications.
• Sintered Ag: Compatible with Au backside metal for high-reliability applications requiring >300°C operating capability.

Reliability & Qualification Summary

Customization Options

• Capacitance: 100pF to 10nF available (contact factory for custom values)
• Voltage: 10V to 50V ratings achievable with dielectric thickness adjustment
• Die size: 300μm to 2mm per side; multi-die arrays for >10nF on single substrate
• Metallization: Au (standard), Al, or Cu with UBM for flip-chip
• Backside: Bare Si, Au, or AuSn
• Screening: Class B (standard), Class S (MIL-PRF-38534) available
• Delivery: Waffle pack, Gel-Pak, tape-and-reel, or sawn wafer on frame

Frequently Asked Questions

How do I model the HACC102S35V500 in my EM simulator?

A certified S-parameter model (100MHz–40GHz, two-port .s2p format) is available under NDA for both wire-bonded and flip-chip mounting configurations. For custom assembly environments, we provide a parameterized 3D EM model (HFSS .aedt or ADS .dsn format) that includes bond wire length, die attach material, and substrate stack-up as user-adjustable parameters. Contact our applications team to request the model library.

Can the HACC102S35V500 survive lead-free reflow if mounted on an interposer?

Yes. When mounted on a ceramic or organic interposer with appropriate underfill, the device withstands standard lead-free reflow profiles (peak 260°C, >217°C for 60-90 seconds). The 2.5μm Au metallization is stable to >300°C. Note that direct PCB attachment without interposer is not recommended due to CTE mismatch with FR-4.

What is the minimum order quantity for prototype evaluation?

Standard evaluation kits include 25 dice in waffle pack with a printed test report for the specific wafer lot. Engineering samples ship within 1-2 weeks. No minimum order quantity for initial evaluation — we want to make it easy to prove the performance advantage in your design.

How do you guarantee Q>300 at 1MHz in production?

Q factor is tested on a per-wafer sample basis (5 dice per wafer, center and 4 corners) using a calibrated impedance analyzer with Cascade Microtech probes. Full-wafer 100% test covers capacitance, leakage, and breakdown voltage on every die. Statistical process control (SPC) charts for Q are maintained, and any wafer with Q<300 at any sample site is quarantined for engineering review. Typical production Q ranges from 350-420 at 1MHz.

Is the HACC series ITAR-free for international projects?

Yes. The HACC series is classified as EAR99 under U.S. Export Administration Regulations. No ITAR restrictions apply. The capacitor is a commercial-off-the-shelf (COTS) component suitable for both commercial and defense applications that do not require ITAR-controlled parts.

Next Steps

1. Request samples — 25-die evaluation kit with test report
2. Download PDK — DRC rules, layer map, and S-parameter models (NDA required)
3. Custom specification — Contact our engineering team with your target C, V, Q, and die size
4. Foundry qualification — Process transfer support for high-volume programs at your preferred fab

Start your evaluation today. Contact us for samples and PDK access.