470pF 20V MOS Capacitor SiO2 Dielectric Low Leakage Capacitor For RF Circuits

Product Specification

HACC471S20V500 470pF 20V MOS Capacitor SiO2 Dielectric for RF Circuits

HACC471S20V500 470pF 20V Single-Layer MIM MOS Capacitor

The HACC471S20V500 is a precision 470pF 20V single-layer MIM (Metal-Insulator-Metal) MOS capacitor fabricated on high-resistivity silicon substrate (>1000 Ω·cm). Built with a thermally-grown SiO2 dielectric and 2.5μm gold metallization, this device is engineered for RF, microwave, and millimeter-wave integrated circuit applications demanding exceptional parametric stability, minimal parasitics, and foundry-grade reproducibility.
With a capacitance density of approximately 1.88 fF/μm² on a compact 500μm * 500μm die, the HACC471S20V500 achieves wafer-level capacitance uniformity with σ < 2%, making it ideal for differential circuit topologies and phased-array systems where channel-to-channel matching is critical.

Key Electrical Specifications

Key Features

• Excellent Uniformity & Stability: Wafer-level capacitance distribution with σ < 2% across 200mm wafers, enabling consistent impedance matching in multi-channel RF front-end modules. Stable parametric performance verified from -55°C to +125°C with < 0.5% capacitance drift over 1000-hour HTOL testing at 125°C.
• Ultra-Low Leakage & High Breakdown Voltage: Thermally-grown SiO2 dielectric delivers leakage current below 1nA at rated 20V bias (equivalent to < 0.5 pA/μm² current density). Breakdown voltage exceeds 60V minimum, providing >3* safety margin for robust operation in power amplifier bias networks and DC blocking applications.
• Low VCC & TCC: Voltage coefficient below 50 ppm/V and temperature coefficient below 30 ppm/°C maintain capacitance accuracy across bias and temperature variations. Critical for sample-and-hold circuits, precision analog filters, and VCO tank networks where capacitance stability directly determines system performance.

Technology & Process

The HACC471S20V500 is manufactured using a single-layer MIM capacitor process on high-resistivity silicon substrate. Key process characteristics include:

• 2.5μm gold metallization — low sheet resistance for minimal ohmic loss, compatible with both wedge and ball wire bonding (25μm gold wire standard)
• Thermally-grown SiO2 dielectric (~20nm) — superior uniformity and defect density compared to deposited oxides, resulting in higher breakdown field (>10 MV/cm) and lower leakage
• High-resistivity silicon substrate (>1000 Ω·cm) — minimizes substrate coupling and eddy current losses at microwave frequencies
• Single-layer MIM structure — near-zero series inductance (< 50pH), eliminating self-resonance below 20GHz
• Backside metallization option — available with Au or AuSn backside metal for conductive epoxy or eutectic die attach

Applications

• RF Impedance Matching: Precision 470pF with tight tolerance enables accurate L-match, Pi-match, and T-match networks in power amplifier, LNA, and antenna front-end modules from 100MHz to 6GHz.
• DC Blocking / AC Coupling: Ultra-low leakage and 60V+ breakdown make it suitable for DC blocking in bias-T networks and inter-stage coupling where DC isolation integrity is critical.
• Sample-and-Hold Circuits: Low VCC (<50ppm/V) and low dielectric absorption ensure minimal voltage droop and pedestal error in high-speed ADC front-ends.
• VCO Tank Resonators: Low TCC (<30ppm/°C) combined with high Q (>200 at 1MHz) minimizes phase noise and frequency drift in voltage-controlled oscillators.
• Charge Pump Filters: Low leakage preserves charge accuracy in PLL loop filters and switched-capacitor circuits.
• Medical Imaging: Suitable for ultrasound transducer tuning and MRI receiver coil matching where parametric stability over temperature is essential.

Quality & Reliability

• 100% wafer-level test: Every die tested for capacitance, leakage current at rated voltage, and breakdown voltage
• Sample-level Q and ESR characterization: Per wafer, per lot
• Reliability qualification: HTOL (1000hr @125°C, 20V bias), HAST (96hr @130°C/85%RH), TC (-55°C to +125°C, 500 cycles)
• Manufacturing: ISO 9001:2015 certified facility, Class 100 cleanroom, full lot traceability
• SPC monitored: Capacitance, leakage, and breakdown voltage tracked with statistical process control
• Documentation: Certificate of Conformance and wafer map included with each shipment

Die & Packaging Information

Frequently Asked Questions

What is the difference between a MIM capacitor and a MOS capacitor?

A MIM (Metal-Insulator-Metal) capacitor uses a dielectric layer sandwiched between two metal plates, offering near-ideal linearity with very low VCC and TCC. A MOS (Metal-Oxide-Semiconductor) capacitor uses the semiconductor substrate as one plate, which introduces a depletion-layer capacitance in series that varies with bias voltage. The HACC471S20V500 uses a true MIM structure, not a traditional MOS capacitor, delivering superior linearity and stability compared to MOS accumulation/inversion capacitors. The "MOS" designation reflects its compatibility with standard CMOS back-end-of-line processes on silicon wafers.

How does the HACC471S20V500 compare to ceramic MLCC capacitors for RF applications?

Compared to ceramic MLCCs of similar capacitance, the HACC471S20V500 offers: (1) near-zero ESL (<50pH vs 200-500pH for MLCCs), eliminating self-resonance below 20GHz; (2) superior TCC (<30ppm/°C vs ±15% for X7R MLCCs); (3) zero piezoelectric effect — no microphonic noise; (4) die-level integration enabling shorter interconnects and reduced parasitics in hybrid or multi-chip modules.

Is the HACC471S20V500 available as Known Good Die (KGD)?

Yes, KGD options are available with additional screening including: extended burn-in, 3-temperature electrical test (-55°C, +25°C, +125°C), and visual inspection per MIL-STD-883. Please contact our sales team for KGD specifications and pricing.

What wire bonding parameters are recommended?

Recommended parameters for 25μm (1mil) gold wire: wedge bonding at 120-150°C stage temperature, 20-30g bond force, 60-80mW ultrasonic power; or ball bonding at 150°C, 15-25g bond force, 40-60mW ultrasonic power. Bond pad is 2.5μm Au, minimum pad opening 80μm * 80μm.

Can the HACC471S20V500 be used above 20GHz?

Yes. With a series inductance below 50pH, the self-resonant frequency (SRF) is well above 30GHz. The single-layer structure ensures resonance-free operation through Ka-band. For millimeter-wave applications above 30GHz, a full 3D EM simulation using our S-parameter model (available on request) is recommended to account for mounting parasitics.

Ordering Information

The HACC471S20V500 is available in production volumes with standard lead time of 2-4 weeks. Custom capacitance values (100pF to 10nF), voltage ratings (10V to 50V), and die sizes are available upon request. Contact our sales team with your target specification for a custom design proposal.
To request samples, a datasheet, or a quotation, please contact us today.