Chongqing Zhongshun Microelectronics Co., Ltd
Products
Manufacturer of a wide range of products which include The overall technical architecture of the 2D ‑ plane SiP is concise and highly implementable,Stacked die SiP supports the integration of various types of dies such as memory...
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| Size | Supports rapid sample customization |
| Intermediate layer | No intermediate layer |
| Number of stacked layers | 1 |
| Chip layout | Placed on the same substrate plane |
| Type | 2D planar SiP |
| TSV | No TSV |
| Model Number | 2D planar SiP |
| Brand Name | Chippack |
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| Intermediate layer | No intermediate layer |
| Number of stacked layers | ≥2 dies |
| Chip layout | Die-to-die vertical stacking |
| Type | Stacked-die SiP |
| Size | Supports rapid sample customization |
| TSV | No TSV |
| Model Number | Stacked-die SiP |
| Brand Name | Chippack |
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| Size | Supports rapid sample customization |
| Intermediate layer | Optional |
| Number of stacked layers | Vertical stacking of ≥2 silicon wafers |
| Chip layout | Vertical TSV Stacking |
| Type | 3D SiP |
| TSV | TSV on the chip itself |
| Model Number | 3D SiP |
| Brand Name | Chippack |
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| Size | Supports rapid sample customization |
| Type | SIP Packaging |
| Brand Name | Chippack |
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| Substrate Type | Organic ABF substrates, HTCC ceramics, LTCC ceramics, silicon interposers, glass interposers |
| Package form | BGA, LGA, QFN, QFP, Ceramic package |
| Size | Supports rapid sample customization |
| Cascading structure | Total Layers, Core Thickness, Dielectric Layer Thickness, Copper Thickness |
| Authentication | Temperature Cycling and Humidity Test Standards |
| Type | 2D planar/Stacked-die/2.5D/3D SiP |
| Model Number | SiP |
| Brand Name | Chippack |
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| Intermediate layer | Silicon / Glass Interposer |
| Number of stacked layers | 1-layer die array |
| Chip layout | laid flat on the silicon interposer |
| Type | 2.5D SiP |
| Size | Supports rapid sample customization |
| TSV | Interposer TSV |
| Model Number | 2.5D SiP |
| Brand Name | Chippack |
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